In the field of electronic systems, there is a continuous need to increase performance and reduce size. This is largely achieved by improving semiconductor wafer manufacturing and semiconductor packaging technologies. Wafer manufacturing involves simultaneously fabricating numerous semiconductor chips as a batch on a silicon wafer using various etching, doping and depositing steps. After the wafer is complete, the chips are separated from one another and packaged.
Semiconductor chips have input/output leads that are connected to external circuitry in order to function as part of an electronic system. Traditionally, a single chip is individually housed in a single-chip package that is connected to other single-chip packages through a printed circuit board, which supplies power to the chips and provides signal routing among the chips. The single-chip package has connection media that is typically an array of metallic leads.
Multi-chip modules (MCM) or hybrid modules that package multiple chips on a common platform are an alternative to single-chip packages. These modules aim to achieve higher packaging density. Conventional multi-chip modules are essentially two-dimensional structures with multiple chips connected to a planar interconnection substrate, which contains traces to supply power and signal transmission. However, since multi-chip modules utilize a planar interconnection substrate as the base, their effectiveness in packaging density is limited. Therefore, in order to create higher density packages, reduce area requirements and shorten signal transmission distances, three-dimensional packages with two, three or more vertically stacked chips are an emerging trend. Three-dimensional packages are particularly suitable for the electronic systems such as supercomputers and other complex systems that require high operating speed and high capacity in very limited space.
Three-dimensional packages generally follow two approaches. In one approach, individual chips are packaged in conventional single-chip packages and then the single-chip packages are vertically stacked and interconnected to one another. In another approach, leads are connected to the chips, and then the exposed leaded chips are vertically stacked and interconnected to one another using peripheral interconnections.
One drawback with many conventional three-dimensional packages is that the vertical interconnections lack the flexibility to accommodate thickness variations of the stacked semiconductors. For instance, chip thickness may vary by 20 microns or more even after backside wafer polishing attempts to planarize the wafer. As a result, vertical interconnections with fixed heights cannot adequately accommodate these thickness variations, and suffer from disoriented, cracked, and open connections, high mechanical stress, and reliability problems.
In summary, conventional three-dimensional packages suffer from numerous deficiencies including large area requirements, inflexible vertical interconnections, limited electrical performance, poor strength, and low reliability. Moreover, conventional three-dimensional packages are often unsuitable for test and repair, manufactured by complicated processes that are impractical for volume production, and too difficult and costly to develop.
In view of the various development stages and limitations in currently available three-dimensional packages, there is a need for a three-dimensional semiconductor package that is cost-effective, reliable, manufacturable, and provides excellent mechanical and electrical performance.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.